The present invention relates to processes for testing integrated circuits, and more particularly, to a process performed by the chip maker for testing digital memory integrated circuits to insure better quality and higher reliability thereof and to eliminate the need for incoming inspection and board level testing by the chip customer. Hereafter, the term "ICs" will be used in place of the term "Integrated Circuits".
During manufacture by the chip maker ICs typically undergo three separate test cycles: (1) in-process testing, such as continuous monitoring of sheets resistivities, junction depths, and other pertinent device parameters, such as current gain and voltage breakdown; (2) a preliminary electrical testing called the wafer-probe test which is performed prior to the scribing and die separation steps; and (3) a detailed final testing of reliability and performance after the completion of the fabrication and packaging steps. The present invention relates to improvements in the last of these three types of testing. A summary of conventional techniques for testing ICs, both digital and linear, is set forth in an article written by Alan B. Grebene and Hans H. Stellrecht beginning at page 8-83 of the book entitled ELECTRONIC ENGINEER'S HANDBOOK, Copyright 1975, by McGraw-Hill, Inc.
The testing of ICs is one of the more expensive and time consuming stages of the manufacturing process. Automatic highspeed testing is practically mandatory to the final testing of modern ICs because a large number of complex tests are required to check even the simplest types of circuits. In addition, most chip customers who assemble the ICs into user systems such as mainframe computers and mini-computers also presently perform a substantial amount of testing of the ICs. It would be desirable to provide chip customers with ICs of significantly better quality and higher reliability than heretofore achieved with conventional chip maker performed final testing processes. This would result in considerable savings to the chip customer by substantially reducing the amount of customer testing required to insure that field failures and down time of systems incorporating such ICs do not exceed acceptably low levels. Further savings would also result to the chip customer because there would be a corresponding reduction in IC inventory throughput time. Such a chip maker performed final test process would have to provide ICs that have already operated in a system environment.
In order to provide a better understanding of the present invention a brief description of conventional testing of ICs by chip makers will be set forth. Thereafter, will follow a brief description of conventional testing of ICs by chip customers. The present invention is primarily intended for use with digital memory ICs, however, it should be understood that it may be extended to other forms of digital ICs as well as to linear ICs.
It is conventional during the final testing cycle to first test the ICs, one by one, for catastrophic failures caused by improper packaging, bonding, metallization, etc. Next the ICs are tested for operating reliability. To reduce the testing time that would otherwise be required under statistical analysis in order to demonstrate reliability with a high degree of confidence, accelerated life tests are typically used. Operation of the ICs for 168 hours at approximately 125.degree. C. near the upper limits of their operating parameters has been accepted by the industry as an adequate test for removing infant mortality. The aforementioned reliability assurance is typically achieved during so-called burn-in of the ICs.
During conventional burn-in, a plurality of ICs are interconnected on high temperature PC boards which are mounted in an oven. Dynamic signals are then applied to each of the ICs through the PC boards to simulate operation. The temperature within the oven, the magnitude of the signals, and the duration of the burn-in are correlated to provide a statistically equivalent processing of 168 hours of operation at 125.degree. C. Failures are accelerated by high temperature and high voltage stress conditions. Therefore, burn-in is a valuable testing step to determine whether the ICs are capable of operating on a long term basis.
After burn-in, it is conventional for the ICs to undergo a number of functional tests to evaluate their performance. One by one each IC is subjected to a series of long and short functional tests. The number and complexity of these functional tests varies from chip maker to chip maker. Long functional testing of digital memory ICs generally involves the pattern testing of each IC on an individual basis. Commonly used routines are checkerboard patterns of 1s and 0s or floating of a 1 or 0 from cell to cell while the adjacent cells are maintained in the opposite state. For larger memories, the generation of these test patterns requires a larger number of functional tests. Generally, the time required for adequate pattern testing increases at a rate which is proportional to the square of the number of bits of storage in the digital memory IC. As the bit storage capacity of a digital memory IC increases, the time required for adequate pattern testing increases at an exponential rate.
Short functional testing of ICs involves the testing of each IC on an individual basis to determine whether it meets the specs set down in the data sheet, e.g. operating speed, and voltage and current parameters. These so-called short functional tests generally require much less testing time than pattern testing. Both the long and short functional tests have heretofore been performed by chip makers in various sequences and at various temperature levels. However, functional testing by the chip maker has not heretofore been performed simultaneously on a large number of ICs.
After the functional tests are completed, the ICs that have satisfactorily undergone all tests are subjected to quality control testing. Sample units undergo one or more of the functional tests for a second time. Thereafter, all the good ICs are shipped to chip customers.
Many chip customers perform an incoming inspection of the ICs received prior to assembling them into user systems. Selected units are tested on an individual basis against data sheet specs, for example. Thereafter, in the case of digital memory ICs, it is common to subject them to board level testing prior to fabricating mainframe computer or mini-computer systems with the same. This involves the mounting of a plurality of digital memory ICs on a PC board in an array and electrically interconnecting them to form a memory board. Suitable drive electronics are usually also mounted on the memory board and are interconnected with the ICs. The memory board is usually coupled to a computer-controlled IC test system. Some chip customers insert these memory boards into a host system. This host system is one of the actual user systems of the type that the memory board will ultimately be inserted into and it has been dedicated for testing use only.
Board level testing is extremely important, because up until this point the system interaction capabilities of the digital memory ICs have not been tested. Single digital memory ICs will often pass all functional tests performed by the chip maker, however, when interacting with thousands of other similar ICs they may experience certain soft errors. A soft error is a random error that does not occur all of the time. Board level testing by chip customer permits the identification of any individual digital memory IC which experiences a single bit of failure due to noise, alpha particles, or marginality during several hours of system testing. These ICs are detected and replaced prior to insertion of the memory board into the ultimate computer system which is to be shipped to the user. Board level testing is thus very important in that it lowers costly down time of the computer system when in the hands of the user and it also reduces the cost of customer engineer calls associated therewith. However, a major portion of the board level testing is pattern testing which is costly and time consuming to perform and which undesirably increases IC inventory through put time.
After board level testing all of the good ICs are assembled into a user system. This system is frequently aged before undergoing a number of tests to verify that it operates as designed. Finally, many chip customers perform a quality control testing of the user systems prior to shipment thereof to the system users.
As previously mentioned, it would be desirable to provide customers with digital memory ICs of significantly better quality and higher reliability than heretofore achieved with conventional chip maker final testing processes. Eliminating the need for a substantial portion of the customer level testing of ICs would result in great economic savings to the chip customer.
In the past, burn-in has been performed by loading a large number of ICs into an oven and by applying dynamic signals to the individual ICs to simulate operating stress conditions at elevated temperatures. The PC boards into which the ICs have been plugged during burn-in have interconnected the ICs such that a defect in any one of the ICs could result in a failure to burn-in others. For example, if an input on a given IC has shorted, this has prevented the appropriate dynamic signals which create stress conditions from being applied to other ICs. These ICs which have not been burned in will often pass all functional tests only to experience an early life failure in a user system. It would be desirable, therefore, to provide a test process performed by the chip maker that would ensure that all ICs shipped to a customer have been burned-in.
In the past, at the chip maker level the system performance or interaction of the ICs has not been monitored in order to detect, for example, individual ICs which are subject to soft errors. Therefore, it would be desirable to provide a process performed by the chip maker of simultaneous or parallel testing a large number of digital memory ICs in board level fashion.
Heretofore, the transition from burn-in testing to functional testing by the chip maker has required the ICs to be loaded into and unloaded from an oven in bulk quantities, and thereafter loaded into and unloaded from a functional test apparatus in one by one fashion. Where the ICs have been functionally tested at different temperature levels, they have generally been loaded and unloaded from different functional test apparatus to eliminate the delay which would otherwise result in waiting for the temperature in a single test apparatus to stabilize at a new level. Thus, parallel burn-in of a large number of ICs followed by serial functional testing thereof has been conventional. While automated handler apparatus exist for facilitating one by one functional testing, such apparatus must be controlled and monitored by an operator whose labor cost must be figured into the sale price of the ICs. Furthermore, each handling step results in a certain percentage of damaged ICs.
If a final test process for digital memory ICs could be developed such that burn-in and long functional testing over a wide temperature range could be performed without handling the ICs inbetween, the chip maker's inventory time could be substantially reduced. In addition, considerable labor savings would result and the percentage of ICs damaged as a result of handling could be significantly reduced.
If the system interaction capability of digital memory ICs is to be tested by the chip maker, some method of limiting the time required for long functional or pattern testing would have to be devised. Large numbers of digital memory ICs, each having a relatively large bit storage capacity, would have to be simultaneously tested in parallel fashion.
U.S. Pat. Nos. 3,412,333; 3,609,547; and 3,656,058 disclose various mechanical apparatus designed for simultaneous burn-in of a plurality of ICs. U.S. Pat. No. 3,710,251 discloses a heat exchanger pedestal for holding a microelectronic circuit on a wafer or chip so that it can be electrically tested at both elevated and depressed temperatures. U.S. Pat. No. 3,761,808 discloses an environmental chamber and test apparatus for automatically performing electrical tests on a plurality of packaged integrated circuits in one by one fashion. U.S. Pat. No. 4,000,460 relates to pattern testing of a plurality of ICs mounted in an array on a PC board. U.S. Pat. Nos. 3,345,567; 3,746,973; 3,781,683; 3,803,483; and 3,842,346 relate to wafer-probe testing of integrated circuits. Finally, U.S. Pat. Nos. 3,039,604; 3,235,797; 3,334,351; 3,492,572; 3,704,418; 3,956,698; 3,979,671; 4,053,833; and 4,168,527 generally pertain to the field of testing of semiconductor devices.